1. Field of the Invention
The present invention relates to a semiconductor circuit device and, more specifically, to a semiconductor circuit device having an internal power supply circuit receiving an external power supply voltage and generating an internal power supply voltage lower than the external power supply voltage.
2. Description of the Background Art
Semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) or SRAMs (Static Random Access Memories) have been proposed as one type of semiconductor circuit devices. Recently, in order to reduce power consumption, a semiconductor memory device including an internal power supply circuit for generating an internal power supply voltage (of 3.3V, for example) by down converting an external power supply voltage (of 5V, for example) has been available.
FIG. 5 is a schematic diagram showing a conventional internal power supply circuit used in a DRAM, for example. Referring to FIG. 5, the conventional internal power supply circuit includes a differential amplifier 60, an N channel MOS transistor 65, a driver transistor 66, P channel MOS transistors 67 to 69, fuses 71 to 73 and an N channel MOS transistor 74. Differential amplifier 60 includes P channel MOS transistors 61 and 62 as well as N channel MOS transistors 63 and 64, receives a reference voltage Vref at the gate of N channel MOS transistor 63 as an inversion input terminal, and supplies an output voltage to node h, using the gate of N channel MOS transistor 64 connected to a node k as a non-inversion input terminal. N channel MOS transistor 65 is connected at one side to N channel MOS transistors 63 and 64, and at the other side, connected to a ground node c, and is turned on/off in response to an enable signal TE. Driver transistor 66 receives at its gate an output voltage from differential amplifier 60, and is connected between an external power supply node al and an internal power supply node b. P channel MOS transistors 67 to 69 have gates connected to ground node c, and connected in series between internal power supply node b and node k. Fuse 71 is connected parallel to P channel MOS transistor 67, fuse 72 parallel to P channel MOS transistor 68, and fuse 73 parallel to P channel MOS transistor 69. Further, fuses 71 to 73 are connected in series between internal power supply node b and node k. N channel MOS transistor 74 is connected between node k and ground node c and receives at its gate a prescribed voltage Vcnt1.
In the above described internal power supply circuit, potential at node k is fed back to differential amplifier 60, whereby differential amplifier 60 controls driver transistor 66 such that the potential at node k is made equal to reference voltage Vref. As a result, the internal power supply circuit supplies an internal power supply voltage intVcc which is higher than the potential at node k by the voltage drop across internal power supply node b and node k, to internal power supply node b.
In the internal power supply circuit described above, reference voltage Vref is set in advance such that the internal power supply voltage intVcc supplied to internal power supply node b is lower than a desired value. Here, when at least one of fuses 71 to 73 is blown off, there is generated a voltage drop by channel resistance of P channel MOS transistors 67 to 69 connected parallel to the disconnected fuse, across internal power supply node b and node k, and by the amount corresponding to the voltage drop, internal power supply voltage intVcc increases.
In this manner, by adjusting number of fuses 71 to 73 to be blown off, the internal power supply voltage intVcc is increased to a desired value.
In the above described internal power supply circuit, it is possible to increase the internal power supply voltage intVcc by blowing off fuses 71 to 73, whereas it is impossible to decrease the internal power supply voltage. Therefore, when the internal power supply voltage intVcc is set higher than the desired value, it is impossible to adjust the internal power supply voltage intVcc to the desired value.
Further, when fuses 71 to 73 are formed of a material having high resistance such as polycrystalline silicon, potential difference between internal power supply node b and node k is increased because of the resistance of fuses 71 to 73, hindering adjustment of the internal power supply voltage intVcc to a desired value.